\subsection{Circuit-Architecture Co-design}
\label{subsec:codesign}

A key component of our research will be the exploration of 
circuit-architecture co-design techniques based on unique 
properties of TFETs. The objective of the techniques will be 
twofold: (a) overcome the limitations of TFETs and (b) enhance 
their benefits in terms of higher energy efficiency. The proposed 
techniques will be evaluated considering appropriate process 
variations across a range of $V_{DD}$ and frequencies. In addition, 
the scalability of the techniques will be analyzed by investigating 
their benefits and trade-offs for different technology nodes. 
Below we describe the proposed research at the circuit and 
architectural levels and discuss the co-design approach that 
we will follow to optimize the energy efficiency, performance
and robustness of TFET-based processors. 

\input{circuit_design}

\input{architecture_design}

\input{cross_layer_optimization}


